This project focuses on the development of key execution units for a 32-bit RISC-V processor using Chisel. As a CPU Designer, the primary goal is to create a set of parameterized and reusable modules, specifically the Arithmetic Logic Unit (ALU), Load Unit, Store Unit, and Branch Unit. These units will be designed to adhere to the RISC-V RV32I instruction set architecture, ensuring compliance and facilitating integration into a larger system-on-a-chip (SoC). The emphasis is on creating highly configurable units that can be adapted to various processor configurations and extended with optional features. This approach promotes code reusability, simplifies future development, and ensures the generated hardware meets the performance requirements of 32-bit RISC-V designs. Thorough testing and documentation are essential components of this project, ensuring the reliability and usability of the developed execution units.
| Sprint | Objective | Status |
|---|---|---|
| Sprint 1 | Minimal Viable Product and ALU | Completed |
| Sprint 2 | Load Unit | Completed |
| Sprint 3 | Store Unit | Completed |
| Sprint 4 | Branch Unit & CPU Core | Completed |
Entire project repository: OctoNyte.
My forked repository: OctoNyte_Adarsh
| Date | Commit Number | Commit Description | Task |
|---|---|---|---|
| 01/27/2025 | Commit | Refactor OctoNyte Execution Units | #15 |
| 02/09/2025 | Commit | Recreated LoadUnit | #36 |
| 03/30/2025 | Commit | Implemented Store Unit for RV32I | #55 |
| 04/23/2025 | Commit | Branch Unit for RV32I | -- |